Semiconductor memory devices, including, for example, read-only memory (ROM), random access memory (RAM), etc., typically include an array of memory cells arranged in rows and columns. Each of the memory cells stores information, often referred to as a bit, in one of two logic states, namely, a logic high state (a logic “1”) and a logic low state (a logic “0”). To access the information stored in a given memory cell, a unique address is utilized. The memory address for each memory cell typically incorporates the particular row and column location of the memory cell in the memory array.
With process technologies pushing well into deep-submicron geometries, IC designers can integrate significant densities of memory and logic together on the same chip. In doing so, they have ushered in the system-on-a-chip (SoC) era. As part of the manufacturing process, a memory device is tested by applying one or more test patterns, often referred to as a test series, to the device and noting any unexpected results as errors. Densely packing the memory cells makes them prone to manufacturing failures. An IC with equal areas of embedded memory and logic (as in the case of SoC technologies) is likely to fail due to manufacturing defects in memory twice as often as it will fail due to defects in logic. Consequently, in SoC ICs having both embedded memory and logic, it is the memory that determines, to a large extent, the overall yield of the ICs.
In order to increase yield, it is known to design a certain amount of redundancy into an IC device having embedded memory. This redundancy is usually provided in the form of spare blocks of memory cells. Accordingly, once an address corresponding to a defective memory cell is identified, it is typically rerouted to a redundant memory cell in the memory array. For this rerouting, the defective memory address is typically programmed into a fuse or antifuse register, the latter being particularly applicable to repair a defective die after encapsulation. In this manner, if an address is provided to a memory device and this address matches a programmed defective address stored in a register of the device, the register, which is associated with a redundant memory location in the array, reroutes the access to the redundant location.
Ideally, there is a redundant memory cell for every memory cell in the memory array. However, the inclusion of redundant memory cells in an IC can undesirably increase the size of the IC. Additionally, overhead logic is generally required to implement a redundant memory architecture. Thus, there is a trade-off between increased yield on the one hand and increased chip size and complexity on the other hand.
Accordingly, there exists a need for improved embedded memory repair techniques which do not suffer from one or more of the above-described problems associated with conventional memory repair techniques.